This invention relates generally to wireless communications, and more particularly, to a system and method of conserving power by using a low speed clock to time the intervals between message frames in a synchronous communication system.
Cell telephones, mobile telephones, and paging systems all communicate to a plurality of roaming wireless units from a central base station, or series of base stations. Many of these roaming wire units, whether acting as transceivers or receivers, are battery powered. Therefore, research continues into improving circuits of these mobile units so that they conserve power, resulting in more reliable communications and longer intervals between battery changes, or recharging.
Time division multiplexing access (TDMA) systems have proven to be popular in organizing communications in a cellular or paging type network. A fundamental similarity between TDMA systems involves the linking all roaming players, or portable units, to a common clock in response to signals from the base station. Time is segmented into a plurality of frames, and each receiver is assigned a specific frame in which to monitor communications from the base station. Therefore, in the simplest forms of a TDMA system, a receiver is only required to monitor communications during a segment of time that is relatively small in comparison to the total time.
It is well known to take advantage of the relatively long rest periods between receiving frames to conserve power in battery operated receiver units. Tiedemann, et al., U.S. Pat. No. 5,392,287, discloses a system of power conservation by de-energizing components of the receiver during rest intervals. Shortly before the receiver's communications frame, power is reapplied to the components, and an initialization is performed. However, the initialization of a receiver can be a power intensive activity. Power may also be wasted if an improperly initialized receiver, or a receiver that is out of synch with the system clock must remain powered to monitor a missed communication occurring in subsequent frames.
Kivari, et al., U.S. Pat. No. 5,291,542 disclose a system of power conservation that involves idling a microprocessor clock output signal during inactive periods. However, the system still needs a high resolution input clock to time the rest intervals between communications, gating the microprocessor clock on and off.
Wieczorek, et al., U.S. Pat. No. 5,150,361, discloses a system of saving power in a TDM radio that involves shutting down nonessential circuits during the rest interval. However, the high resolution reference oscillator is left on to perform the timing function.
Murai, et al., U.S. Pat. No. 5,274,843, discloses a system of saving power in a paging circuit which involves shutting off some elements of the receiver until a preamble is detected. Once again, high resolution timing circuitry must remain enabled during the rest period to detect preamble message signals.
As is well known in the art, the power consumption of a CMOS circuit is reduced by reducing its frequency of operation. That is, the power consumption of a CMOS part is proportional to the system clock enabling the circuit. Hongo, U.S. Pat. No. 5,461,652, discloses a system of using a low speed clock, during wait states, to operate the system. Cooney et al, U.S. Pat. No. 4,254,475, disclose a dual frequency clock system that uses a low speed clock during periods of inactivity. Frane, U.S. Pat. No. 5,025,387, discloses a dual frequency clock system to reduce power consumption during periods of inactivity. However, all three of the above-mentioned patents disclose systems where the power conserving unit need not perform the timing necessary to wake itself up. That is, the enable signal which turns the system on, enabling a high speed clock, is delivered from outside the apparatus.
It would be advantageous if a player in a synchronous communication system could conserve power by de-energizing the high resolution clock, or oscillator, required for modulation or demodulation of communication messages, during the periods of inactivity between messages.
It would be advantageous if the rest interval between communication frames in a synchronous communication system could be timed with a low speed, and therefore, low power clock. It would also be advantageous if the communications player could maintain rest interval timing with the resolution of a high speed clock by using a low speed clock.
Accordingly, in a wireless system of communicating players, having a predetermined rest interval between player communications, wherein the rest interval includes a predetermined first wait time and a predetermined second wait time, significantly longer than the first wait time, and players use a high speed clock to execute procedures during a communication, a method for a player to conserve power by using a low speed clock in the measurement of the rest time interval is provided. The method comprises the steps of:
a) using the high speed clock to measure the first wait time, whereby a precisely times rest interval maximizes the possibility of communication between players; PA1 b) de-energizing the high speed clock, whereby power consumption is reduced; and PA1 c) using the low speed clock to measure the second wait time, whereby a precise measurement of the rest interval is made with a minimal use of power.
In one aspect of the invention, the rest interval includes a predetermined third wait time, and includes the step, following the measurement of the second wait time in Step c), of using the low speed clock to measure the third wait time. During the third wait time, another step applies power to the high speed clock, stabilizing the high speed clock to operate at a selected period.
One aspect of the invention divides the rest interval by the low speed clock period to obtain a whole number of low speed clock periods, n.sub.0, and a remainder approximately equal to the first wait time. The method then includes the step of multiplying the low speed clock period by a predetermined whole number, n.sub.3, to measure the third wait time, and Step b) includes multiplying the low speed clock period by n.sub.2, where n.sub.2 =n.sub.0 -n.sub.3, to measure the second wait time.
One aspect of the invention includes the step of obtaining an n.sub.0 value such that the first wait time is greater than, or equal to the low speed clock period, whereby the first wait time is large enough that the rest interval is measured with a non-synchronous clock.
In a wireless network of communicating player units having a predetermined rest interval between player unit communications, wherein the rest interval includes a predetermined first wait time and a predetermined second wait time, significantly longer than the first wait time, a system for a player unit to conserve power between communications is also provided. The system comprises a high speed clock having an input to energize the high speed clock, and an output operatively connected to communication circuits to provide a high speed clock period, T.sub.1, whereby the clock is used to execute procedures during a communication. The system comprises a low speed clock with a rate of power consumption that is low compared to the high speed clock, and having an output to provide a low speed clock period, T.sub.2. The system comprises a first counter circuit having an input operatively connected to the high speed clock output to determine the first waiting time by counting a predetermined number, n.sub.1 of high speed clock periods. The first counter circuit also has an output to provide a first wait time signal after the first wait time is counted.
The system also comprises a second counter circuit having an input operatively connected to the low speed clock output to determine the second wait time by counting a predetermined number, n.sub.2 of low speed clock periods. The second counter circuit has an output to provide a second wait time signal after the second wait time is counted.
The system also comprises a power controller circuit having a first input operatively connected to the first counter circuit output, a second input operatively connected to the second counter circuit output, and an output operatively connected to the high speed clock input, to de-energize the high speed clock during the counting of the second wait time, and to energize the high speed clock when the second wait time signal is received. In this manner, the rest interval is precisely timed despite the high speed clock being de-energized for a majority of the rest interval.
In one aspect of the invention the rest interval includes a third wait time and the system further comprises a third counter circuit having a first input operatively connected to the power controller output to trigger the counting of the third wait time when the high speed clock is energized. The third counter also has a second input operatively connected to the low speed clock output. The third counter determines the third waiting time by counting a predetermined number, n.sub.3 of low speed clock periods. The third counter circuit has an output to provide a third wait time signal after the third wait time is counted.
The system includes a gating circuit having a first input operatively connected to the high speed clock output, and a second input operatively connected to the third counter circuit output, the gating circuit has an output to provide the high speed clock, enabling the high speed clock period when the third wait time signal is received. In this manner, the high speed clock is allowed to stabilize before being enabled to activate and manage communication circuits.